Computer Architecture Scale Models

Photonic Network-on-Wafer for Multi-Tile GPUs: From Architecture to Hardware Implementation

Datacenter Monitoring for Improving Insight and Efficiency

Dependable performance on many-thread processors (DPMP)

Forward Slice Core

High-Speed Architectural Simulation of ARM-based Systems

Load Slice Core: A Power and Cost-Efficient Microarchitecture for the Future

Computer architecture

Doctoral project Ajeya Naithani

Doctoral project Almutaz Adileh

Doctoral project Benyamin Eslami

Doctoral project Cecilia González-Álvarez

Doctoral project Frederick Ryckbosch

Doctoral project Jaime Roelandts

Doctoral project Jeroen De Wachter

Doctoral project Kenzo Van Craeynest

Doctoral project Kristof Du Bois

Doctoral project Lu Wang

Doctoral project Osman Allam

Doctoral project Sam Van den Steen

Doctoral project Sander De Pestel

Doctoral project Trevor Carlson

Doctoral project Xia Zhao

Doctoral project Yuxi Liu

Low-Complexity and Power-Efficient Processor Architectures

Reliability-Aware Management in Hybrid Memories: Evaluation through Scale-Model Simulation

Scaling Performance in Multi-Chip GPU Systems: Challenges and Opportunities

Adressing Energy in Parallel Technologies

Alliance Research Group: Optimizing the Performance and Efficiency of Modern Programming Languages

Analytical ability modeling of heterogeneous multicore processors

Analytical performance modeling of chip multiprocessors

Automatic stress mark generation for the evaluation of computer systems

BOF-ZAP professorship in computer architecture

Dynamic Power Management in Heterogeneous Multi-Core Processors

Efficient microprocessor design through machine learning

Fault-tolerant network-on-chip design

Flanders High Performance Computing Lab

Heterogeneous Data Centers

Just-in-Time Data Structures

Micro-architectural independent performance modeling application-specific processors

Multi-objective compiler optimization space exploration

Resource Management in Power-Constrained Computing Systems

Sustainable computer architecture

Automatic generation of mini benchmarks

University of Toronto - UGent Partnership

BOF-ZAP professorship in computer architecture

Characterization of computer programs for the efficiency evaluation of microprocessor systems.