Fault-tolerant network-on-chip design

01 March 2017 → 30 June 2020
Regional and community funding: Special Research Fund
Research disciplines
  • Natural sciences
    • Computer system architecture
    • Performance modelling
    • System software and middleware
    • Computer architecture and networks not elsewhere classified
    • Language processors
    • Programming languages and technologies
  • Engineering and technology
    • Computer architecture and organisation
    • Memory structures
    • Performance evaluation, testing and simulation of reliability
    • Processor architectures
    • Computer hardware not elsewhere classified
Network-on-chip computer architecture GPU
Project description

Network-on-chip (NoCs) possess high flexibility and scalability and thus represent an efficient approach for solving the communication problem in multi-core chips. However, it brings about reliability challenges. We focus on providing efficient strategies for mitigating both transient and hard errors in the NoC, for which we will develop fault-tolerant cache coherence protocols.