Dynamic Power Management in Heterogeneous Multi-Core Processors

01 January 2017 → 31 December 2020
Research Foundation - Flanders (FWO)
Research disciplines
  • Natural sciences
    • Computer system architecture
    • Performance modelling
    • System software and middleware
    • Computer architecture and networks not elsewhere classified
  • Engineering and technology
    • Computer architecture and organisation
    • Memory structures
    • Performance evaluation, testing and simulation of reliability
    • Processor architectures
    • Computer hardware not elsewhere classified
heterogeneous multicore processors Power management computer architecture
Project description

Heterogeneous processors (e.g., ARM’s big.LITTLE) provide flexibility in power-constrained environments by executing applications on the ‘big’ high-performance core when there is available power budget and on the ‘little’ core when power is limited. This project explores dynamic power management in heterogeneous chip-multiprocessors (HCMPs) with per-core DVFS, optimizing performance within a power limit per thermally significant time period. We decompose the overall problem statement into three sub-problems: (i) power budget partitioning; (ii) criticality-aware power allocation; and (iii) identification of the optimal operating point (core type, frequency setting, SMT concurrency level) per thread.