Research Explorer

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Researcher

Stéphane Burignat

Awards & Distinctions

26 Results

2014

A technology based complexity model for reversible Cuccaro ripple-carry adder

Stéphane BurignatAlexis De Vos

A2 Journal Article in JOURNAL OF LOW POWER ELECTRONICS

Designing garbage-free reversible implementations of the integer cosine transform

Alexis De VosStéphane BurignatRobert GlückTorben Ægidius MogensenHolger Bock AxelsenMichael Kirkedal ThomsenEva RotenbergTetsuo Yokoyama

A1 Journal Article in ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS

Energy consumption by reversible circuits in the 130 nm and 65 nm nodes

Stéphane BurignatAlexis De Vos

A2 Journal Article in JOURNAL OF LOW POWER ELECTRONICS

2012

Garbageless reversible implementation of integer linear transformations

Stéphane BurignatKenneth VermeirschAlexis De VosMichael Thomsen

Reversible implementation of a discrete integer linear transformation

Alexis De VosStéphane BurignatMichael Kirkedal Thomsen

A1 Journal Article in JOURNAL OF MULTIPLE-VALUED LOGIC AND SOFT COMPUTING

2011

Interfacing reversible pass-transistor CMOS chips with conventional restoring CMOS circuits

Stéphane BurignatMichael Kirkedal ThomsenMichal KlimczakMariusz OlczakAlexis De Vos

Reversible computation, a quantum-inspired low-consumption viable technology?

Stéphane Burignat

Test of a majority-based reversible (quantum) 4 bits ripple-carry adder in adiabatic calculation

Stéphane BurignatAlexis De Vos

Towards the limits of cascaded reversible (quantum-inspired) circuits

Stéphane BurignatMariusz OlczacMichal KlimczakAlexis De Vos

2010

Analog/RF performance of sub-100 nm SOI MOSFETs with non-classical gate-source/drain underlap channel design

A KrantiR RashmiStéphane BurignatJ-P RaskinGA Armstrong

Conduction par pièges dans les films minces de dioxyde de silicium

Stéphane Burignat

Experimental study of transconductance and mobility behaviors in ultra-thin SOI MOSFETs with standard and thin buried oxides

T RudenkoV KilchytskaStéphane BurignatJ-P RaskinF AndrieuO FaynotY Le TiecK LandryA NazarovVS Lysenko et al.

A1 Journal Article in SOLID-STATE ELECTRONICS

Reversible implementation of a disrete linear transformation

Alexis De VosStéphane BurignatMichael Thomsen

Substrate impact on threshold voltage and subthreshold slope of sub-32 nm ultra thin SOI MOSFETs with thin buried oxide and undoped channel

Stéphane BurignatD FlandreMK Md ArshadV KilchytskaF AndrieuO FaynotJ-P Raskin

A1 Journal Article in SOLID-STATE ELECTRONICS

2009

Drain/substrate coupling impact on DIBL of ultra thin body and BOX SOI MOSFETs with undoped channel

Stéphane BurignatMKM ArshadJ-P RaskinV KilchytskaD FlandreO FaynotP ScheiblinF Andrieu

Substrate effects in sub-32 nm ultra thin SOI MOSFETs with thin buried oxide

Stéphane BurignatDenis FlandreValeriya KilchytskaFrançois AndrieuxOlivier FaynotJean-Pierre Raskin

Transconductance and mobility behaviors in UTB SOI MOSFETs with standard and thin BOX

Tamara RudenkoValeriya KilchytskaStéphane BurignatJean-Pierre RaskinFrançois AndrieuOlivier FaynotA. NazarovV.-S. LysenkoDenis Flandre

Underlap channel UTBB MOSFETs for low-power analog/RF applications

A KrantiStéphane BurignatJ-P RaskinGA Armstrong

2007

Retention in metal-oxide-semiconductor structures with two embedded self-aligned Ge-nanocrystal layers

S DuguayStéphane BurignatP KernJJ GrobA SouifiA Slaoui

A1 Journal Article in SEMICONDUCTOR SCIENCE AND TECHNOLOGY

Spatial and energetical profiles of defects extracted from ultra-low level trap-assisted leakage current in non-volatile floating thin tunnel oxide memory devices by using direct and floating gate technique measurements

Stéphane BurignatC PlossuP Boivin

A1 Journal Article in JOURNAL OF NON-CRYSTALLINE SOLIDS

Ultra-fine grain reconfigurability using CNTFETs

I O'ConnorJ LiuD NavarroI HassouneStéphane BurignatF Gaffiot

2005

EEPROM retention time extrapolation from floating gate SILC measurements

Stéphane BurignatNicolas BabouxCarole PlossuPhilippe Boivin

Structural properties of Ge-implanted SiO2 layers and related MOS memory effects

S DuguayA SlaouiJJ GrobM KanounStéphane BurignatA Souifi

A1 Journal Article in MATERIALS SCIENCE AND ENGINEERING B-SOLID STATE MATERIALS FOR ADVANCED TECHNOLOGY

2003

Capacitance and current-voltage simulation of EEPROM technology highly doped MOS structures

S CrociC PlossuStéphane BurignatP Boivin

A1 Journal Article in JOURNAL OF MATERIALS SCIENCE-MATERIALS IN ELECTRONICS

Quantitative study of charge trapping in SiO2 during bipolar Fowler-Nordheim injection

C BusseretN BabouxC PlossuStéphane BurignatP Boivin

A1 Journal Article in JOURNAL OF NON-CRYSTALLINE SOLIDS

Towards a model linking tunnel oxide degradation to programming window closure in EEPROM cells

N BabouxC BusseretC PlossuStéphane BurignatB BallandP Boivin

A1 Journal Article in JOURNAL OF NON-CRYSTALLINE SOLIDS