Research Explorer

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Onderzoeker

Henk Neefs

Prijzen & Erkenningen

26 Resultaten

2000

A Technique for High Bandwidth and Deterministic Low Latency Load/Store Accesses to Multiple Cache Banks.

Henk NeefsHans VandierendonckKoen De Bosschere

Designing a branch predictor for a block structured architecture

Frederik HabilsHenk NeefsKoen De Bosschere

Early design stage exploration of fixed-length block structured architectures.

Lieven EeckhoutHenk NeefsKoen De Bosschere

A1 Artikel in een tijdschrift in JOURNAL OF SYSTEMS ARCHITECTURE

Estimating IPC of a Block Structured Instruction Set Architecture in an Early Design Stage. Parallel Computing: Fundamentals and Applications ;.

Lieven EeckhoutHenk NeefsKoen De Bosschere

On the Feasibility of Fixed-Length Block Structured Architectures.

Lieven EeckhoutKoen De BosschereHenk Neefs

Optoelectronic interconnects for integrated circuits. Achievements 1996-2000.

Performance Analysis through Synthetic Trace Generation

Lieven EeckhoutKoen De BosschereHenk Neefs

1999

Exploitable levels of ILP in future processors.

Henk NeefsKoen De BosschereJan Van Campenhout

A1 Artikel in een tijdschrift in JOURNAL OF SYSTEMS ARCHITECTURE

Investigating the Implementation of a Block Structured Processor Architecture in an Early Design Stage.

Lieven EeckhoutHenk NeefsKoen De BosschereJan Van Campenhout

On the Benefits of a Block Structured Instruction Set Architecture.

Lieven EeckhoutHenk NeefsKoen De Bosschere

On the Organization and Implementation of a Fixed-Length Block Structured Instruction Set Architecture.

Lieven EeckhoutHenk NeefsKoen De BosschereJan Van Campenhout

1998

A Quantitative Study of Optical Interconnects at the L2-cache to Main Memory Level in a Uniprocessor

Henk NeefsP VANHEUVENJan Van Campenhout

Aspects of a Fixed-Length Block Structured Instruction Set to Improve Loop Performance

Lieven EeckhoutHenk NeefsKoen De BosschereJan Van Campenhout

ESCAPE: Environment for the Simulation of Computer Architectures for the Purpose of Education

Jan Van CampenhoutPeter VerplaetseHenk Neefs

Improving Loop Performance on a Block Structured Architecture through Predication

Lieven EeckhoutHenk NeefsKoen De BosschereJan Van Campenhout

Latency Requirements of Optical Interconnects at Different Memory Hierarchy Levels of a Computer System

Henk NeefsP VANHEUVENJan Van Campenhout

Latency requirements of optical interconnects at different memory hierarchy levels of a computer system

Henk NeefsPim Van HeuvenJan Van Campenhout

Optical Interconnects at the L2 Cache to Main Memory Level in a Computer System and the Effect of Prefetching

Henk NeefsP VANHEUVENJan Van Campenhout

1997

An Analytical Model for Performance Estimation of Modern Data-Flow Style Scheduling Microprocessors

Henk NeefsKoen De BosschereJan Van Campenhout

Issues in Compilation for Fixed-Length Block Structured Instruction Set Architectures

Henk NeefsKoen De BosschereJan Van Campenhout

Microarchitectural Issues of a Fixed Length Block Structured Instruction Set Architecture

Henk NeefsKoen De BosschereJan Van Campenhout

1996

A C++ Simulator modelling a modern data-flow scheduling Microprocessor

Henk NeefsKoen De BosschereJan Van Campenhout

A Microarchitecture for a fixed length Block Structured instruction set Architecture

Henk NeefsJan Van Campenhout

Simulating a Modern Data-flow Scheduling Microprocessor in C++

Henk NeefsKoen De BosschereJan Van Campenhout

1995

Arrays of light emitting diodes with integrated diffractive microlenses for board-to-board optical interconnect applications: design, modelling and experimental assessment.

Bart DhoedtPeter De DobbelaereJohan BlondellePeter Van DaelePiet DemeesterHenk NeefsJan Van CampenhoutRoel Baets

Hoofdstuk in een boek in CLEO EUROPE '94

1994

A Optoelectronic 3-D Field Programmable Gate Arra. , Prague, 1994.

Jo DepreitereHenk NeefsHerwig Van MarckJan Van CampenhoutRoel BaetsBart DhoedtHugo ThienpontI VERETENNICOFF