Research Explorer

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Onderzoeker

Elias Vansteenkiste

Prijzen & Erkenningen

23 Resultaten

2019

CRoute: a fast high-quality timing-driven connection-based FPGA router

Dries VercruyceElias VansteenkisteDirk Stroobandt

2018

Hierarchical force-based block spreading for analytical FPGA placement

Dries VercruyceElias VansteenkisteDirk Stroobandt

How preserving circuit design hierarchy during FPGA packing leads to better performance

Dries VercruyceElias VansteenkisteDirk Stroobandt

A1 Artikel in een tijdschrift in IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS

2017

Liquid : high quality scalable placement for large heterogeneous FPGAs

Dries VercruyceElias VansteenkisteDirk Stroobandt

2016

A fully parameterized virtual coarse grained reconfigurable array for high performance computing applications

Amit KulkarniElias VansteenkisteDirk StroobandtAndreas BrokalakisAntonios Nikitakis

EXTRA : towards the exploitation of eXascale technology for reconfigurable architectures

Dirk StroobandtAna Lucia VarbanescuCatalin Bogdan CiobanuMuhammed Al KadiAndreas BrokalakisGeorge CharitopoulosTim TodmanXinyu NiuDionisios PnevmatikatosAmit Kulkarni et al.

Liquid : fast placement prototyping through steepest gradient descent movement

Elias VansteenkisteSeppe LendersDirk Stroobandt

New FPGA design tools and architectures

Elias VansteenkisteDirk Stroobandt

Runtime-quality tradeoff in partitioning based multithreaded packing

Dries VercruyceElias VansteenkisteDirk Stroobandt

2015

Analyzing the divide between FPGA academic and commercial results

Elias VansteenkisteAlireza KavianiHenri Fraisse

EXTRA : towards an efficient open platform for reconfigurable high performance computing

Catalin Bogdan CiobanuAna Lucia VarbanescuDionisios PnevmatikatosGeorge CharitopoulosXinyu NiuWayne LukMarco D SantambrogioDonatella SciutoMuhammed Al KadiMichael Huebner et al.

Estimating circuit delays in FPGAs after technology mapping

Berg SeverensElias VansteenkisteKarel HeyseDirk Stroobandt

FASTER: facilitating analysis and synthesis technologies for effective reconfiguration

D PnevmatikatosK PapadimitriouT BeckerP BöhmA BrokalakisKarel BruneelC CiobanuTom DavidsonG GaydadjievKarel Heyse et al.

A1 Artikel in een tijdschrift in MICROPROCESSORS AND MICROSYSTEMS

Identification of dynamic circuit specialization opportunities in RTL code

Tom DavidsonElias VansteenkisteKarel HeyseKarel BruneelDirk Stroobandt

A1 Artikel in een tijdschrift in ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS

Logic Gates in the routing network of FPGAs (Abstract Only)

Elias VansteenkisteBerg SeverensDirk Stroobandt

2014

Parameterised FPGA reconfigurations for efficient test set generation

Alexandra KourfaliElias VansteenkisteDirk Stroobandt

TPaR: place and route tools for the dynamic reconfiguration of the FPGA's interconnect network

Elias VansteenkisteBrahim Al FarisiKarel BruneelDirk Stroobandt

A1 Artikel in een tijdschrift in IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS

2013

A connection-based router for FPGAs

Elias VansteenkisteKarel BruneelDirk Stroobandt

A novel tool flow for increased routing configuration similarity in multi-mode circuits

Brahim Al FarisiElias VansteenkisteKarel BruneelDirk Stroobandt

Efficient implementation of virtual coarse grained reconfigurable arrays on FPGAS

Karel HeyseTom DavidsonElias VansteenkisteKarel BruneelDirk Stroobandt

Efficient implementation of virtual coarse grained reconfigurable arrays on FPGAs

Karel HeyseTom DavidsonElias VansteenkisteKarel BruneelDirk Stroobandt

2012

A connection router for the dynamic reconfiguration of FPGAs

Elias VansteenkisteKarel BruneelDirk Stroobandt

Maximizing the reuse of routing resources in a reconfiguration-aware connection router

Elias VansteenkisteKarel BruneelDirk Stroobandt