01 March 2017 → 30 September 2021
Regional and community funding: Special Research Fund
Engineering and technology
- Design theories and methods
FPGA CAD Tools Placement and Routing (P&R) Hardware Acceleration Parallelization
FPGA design compilation takes too much time to allow an efficient design turnaround time. Our overall high-level goal is to significantly reduce the FPGA design compilation time by efficiently parallelizing placement and routing algorithms onto a GPU/FPGA (hardware acceleration), in order to bring benefit to the development of FPGA CAD tools and the design of FPGA based systems.