Problem: FPGA's are gei''ntegreerde circuits (IC) with a regular structure of adaptable functional blocks, embedded in an adjustable interconnection network. Because of their flexibility, they are often used in embedded systems. However, the design of new FPGA architectures is a difficult task that takes a lot of time. In the search for new functional blocks of the interconnection network to be re-dimensioned changes each time a block functioned. This allows the study difficult because this dimensioning is a time-consuming and iterative process.