To support the increasing demands for higher data rates in datacenter interconnects, next generation Ethernet standard (1.6 TbE) foresees 8 lanes carrying 224 Gbps. The electronics to support these high data rates are yet to be developed. One of the critical building blocks in these transceivers is the clock and data recovery circuit (CDR), which reconstructs a clock signal to sample the incoming data stream at the most optimal point. This project will focus on new architectures for these CDRs that overcome imperfections of the used 4-level modulation format. Typically, the levels are unevenly spaced and delay variations occur between the levels due to linearity limitations. To recover the data, the signal will be first quantized before it is sampled. After quantization, the signal will be reconstructed using a multi-loop CDR architecture allowing distribution of a low speed clock and fine tune the delay locally to adjust the delay between the different levels. The effect on how these multiple loops interact, and how to control them to ensure optimal signal reception will be studied. To reduce the power consumption of the CDR, the phase error used to align the clocks will be subsampled. This technique was proven very effective for 2-level signals, but hasn’t been studied for 4-level signaling. Eventually, subsampling can almost half the total power consumption of the CDR. In the end, these techniques will be validated by integrating them in a demonstrator chip.