Although today's electronic systems implement most of their functionality in the digital domain, several analog operations, above all the analog-to-digital conversion (ADC), remain necessary when interfacing with physical-world applications. An example is data communication where ever higher bandwidths are required. A basic problem though is that traditional analog solutions based on opamps and comparators are limited in performance by their intrinsic accuracy-speed-power trade-offs due to noise and mismatch, and do not shrink in chip area in scaled CMOS technologies. Highly-digital time-encoding converter solutions (e.g. VCO-based ADCs) have recently emerged as alternatives that scale better and intrinsically have the potential of much better area and power efficiency. But their overall performance still lags behind the traditional circuits and is still far below the theoretical limits. Therefore, the current way of building time-encoding ADCs needs to be rethought to bridge the 200x power efficiency gap between the state of the art and the theoretical noise limit. The project's goal is to close this gap by fundamentally exploring innovative digitally-boosted circuits and architectures with drastically increased bandwidth/power performance. A fundamental study of the optimal analog-digital partitioning will lead to novel structures to be explored and prototyped in silicon, including cascaded and stochastic converters.