Research Explorer

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Project

Scalar Vector Runahead to Accelerate Graph Workloads on Edge Processors

Outputs and Outcomes

Code

01CD01825

Duration

01 April 2025 → 30 September 2025

Funding

Regional and community funding: Special Research Fund

Promotor

Lieven Eeckhout

Fellow

Jaime Roelandts

Research disciplines

Natural sciences
- Computer system architecture

Keywords

runahead hardware prefetching computer architecture

Project description

Scalar Vector Runahead (SVR) extracts high memory-level parallelism on power-efficient stall-on-use in-order cores by piggybacking on existing instructions executed on the processor leading to future irregular memory accesses. SVR speculatively executes multiple transient, independent, parallel instances of memory accesses and their chains initiated from different values of a predicted induction variable to move mutually independent memory accesses next to each other to hide dependent stalls.

English

Dutch

English

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