Scalar Vector Runahead (SVR) extracts high memory-level parallelism on power-efficient stall-on-use in-order cores by piggybacking on existing instructions executed on the processor leading to future irregular memory accesses. SVR speculatively executes multiple transient, independent, parallel instances of memory accesses and their chains initiated from different values of a predicted induction variable to move mutually independent memory accesses next to each other to hide dependent stalls.