Project

Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration

Acronym
FASTER
Code
41J01211
Duration
01 September 2011 → 30 November 2014
Funding
European funding: framework programme
Research disciplines
  • Natural sciences
    • Applied mathematics in specific fields
Keywords
reconfigurable computing
 
Project description

Extending product functionality and improving their lifetime requires additional features to satisfy the growing customer's needs as well as new market and technology trends. Fro example, a network Intrusion Detection System needs to scan all incoming network packets for suspicious content. The scanning has to be at "line-speed" so that the monitored communication links are not slowed down, while the list of threats to check for is extended and updated on a daily basis. Reconfigurable logic allows the definition of new functions to be implemented and dynamically instantiated in hardware units combining hardware speed and efficiency with the ability to adapt and cope in a cost effective way with expanding functionality. For the intrusion Detection System example, the new rules can be hardcoded into the reconfigurable logic, thus retaining the high performance, while providing the necessary adaptability and extensibility to new threats.

Faster will implement a complete methodology to allow designers to easily implement and verify a system specification on a platform that includes one or more general purpose processor(s) combined with multiple acceleration modules implemented on one or multiple reconfigurable devices.