Pïezoelectronic Transduction Memory Device

01 December 2015 → 31 May 2019
European funding: framework programme
Research disciplines
  • Natural sciences
    • Optical physics not elsewhere classified
material sciences
Project description

Computer clock speeds have not increased since 2003, creating a challenge to invent a successor to CMOS technology able to resume performance improvement. The key requirements for a viable alternative are scalability to nano scale dimensions – following Moore’s Law – and simultaneous reduction of line voltage in order to limit switching power. Achieving these two aims for both transistors and memory allows clock speed to again increase with dimensional scaling, a result that would have great impact across the IT industry if realized. We propose to demonstrate an entirely new low-voltage, memory element that makes use of internal transduction in which a voltage state external to the device is converted to an internal acoustic signal that drives an insulator-metal transition. Modelling based on the properties of known materials at device dimensions on the 15 nm scale predicts that this mechanism enables device operation at voltages an order of magnitude lower than CMOS technology while achieving 10GHz operating speed; power is thus reduced two orders.