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Project
An Optical Phase locked loop for low phase noise sub-terahertz signal generation on a silicon nitride photonic platform
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Project Team
Organisations
Outputs and Outcomes
Publications
A duty-cycle switching 30-Gb/s burst-mode CDR with 1.6-ns locking time in 28-nm CMOS
Xin Wang
Achim Vandierendonck
Bruno Govaerts
Tinus Pannier
Warre Geeroms
Caro Meysmans
Johan Bauwelinck
Guy Torfs
A1
Journal Article
in
IEEE JOURNAL OF SOLID-STATE CIRCUITS
2025