In this project we study the implementation of optical input/output (I/O) for memory/compute chips for future high-performance computing (HPC) systems The system architecture we propose addresses the shortcomings of today’ HPC interconnect, which relies on electronic switches interconnected by high-speed optical transmitters and receivers This requires a conversion of the signal from the optical domain to the electrical domain and back, which introduces high power consumption and latency of the system In this project we will develop optical transmitters and receivers that are compatible with the use of an optical switch fabric instead of an electronic switch fabric (thereby substantially reducing power consumption and latency of the system) and that can be co-packaged with the compute/memory chips for ultimate performance  Very high I/O speeds of 16 terabit/s (or 1600000000000 bits/ second) per transmitter/receiver chip are envisioned, making this a future-proof approach to high-performance computing