Digital PLL techniques for multi-gigabit clock and data recovery with low power consumption in fiber networks

01 January 2014 → 31 December 2017
Regional and community funding: IWT/VLAIO
Research disciplines
  • Engineering and technology
    • Communications
    • Communications technology
Digital PLL techniques data traffic band width
Project description

During the last couple of years, data traffic has been rising exponentially and it is predicted that this growth is not going to end anytime soon. This is due to new broadband applications in the field of entertainment, commerce, industry, health care and social interactions which demand increasingly higher data rates and quality of the networks and Information and Communications Technology (ICT) infrastructure. In addition, high definition video streaming and cloud services will continue to push the demand for bandwidth. In the current architecture of the internet, end-users connect to the public network using the access network of an internet service provider. Today, this access network uses Passive Optical Network (PON) technologies because optical fiber is highly energy efficient for high data rates. Still, research has shown that the power consumption of communication networks is taking up a significant and growing share of the total global power consumption. Therefore, over the past few years, a stronger awareness has risen with respect to this negative environmental impact of massive power consumption in communication networks. This has led to the foundation of the GreenTouch consortium in 2010, which focuses on the problem of increasing data rates while reducing the economical and environmental impact. Its mission is to show that the energy efficiency of communication networks could be improved by a factor of 1000 by 2020, compared to the GreenTouch-defined baseline network which was built using the most energy efficient equipment available in 2010. An important part of an optical receiver in a PON access network are Clock and Data Recovery (CDR) circuits. These CDR circuits are currently implemented with bulky and power hungry analog sub-blocks and thus have a lot of room for improvement. In this dissertation, low-power subsampling All-Digital Clock and Data Recovery (AD-CDR) techniques are presented as an answer to the various challenges next-generation networks are facing. To demonstrate this, a 25Gb=s Phase Locked Loop (PLL)-based All-Digital Clock and Data Recovery (AD-CDR) circuit prototype was implemented in an advanced CMOS technology (40nm). Thanks to the highly digital architecture, the active die area is very compact and only occupies 0:050mm2 which is significantly smaller than competing work. The power efficiency of the CDR core is 1:8 pJ=b which is also better than the state-of-the-art. Additionally, the All-Digital Clock and Data Recovery (AD-CDR) is highly adaptable: i.e. the characteristics of the loop filter can be tuned to satisfy multiple jitter tolerance specifications. Moreover, the operating range can be varied from 12:5Gb=s to 25Gb=s, which is the broadest operating range of any digital CDR that does not use a highquality, multi-gigahertz reference clock. Due to the truly digital frequency adaptable nature, the power consumption decreases linearly with the data rate and hence an excellent power efficiency is maintained over the entire operating range: e.g. at 25Gb=s the power consumption is 46mW while at 12:5Gb=s this is 23mW. Furthermore, the AD-CDR is also able to capture burst mode data. The burst mode operation of the CDR is realized thanks to the lack of frequency drift between bursts and the possibility to adapt the Digital Loop Filter (DLF) parameters to obtain a large loop bandwidth. These features enable short settling times. As a result, the AD-CDR does not require a high-accuracy reference clock nor a start-of-burst signal. Only the Digitally Controlled Oscillator (DCO) needs a 1-time only calibration to ensure that its frequency is in the vicinity of the line rate. This significantly simplifies the integration of the component in a system. The dissertation is composed of seven chapters and one appendix: Chapter 1 discusses the impact of increasing data rates and the desire to reduce power consumption in communication networks. Subsequently, the current core-metro-access architecture is presented and typical numbers are given to show why the power consumption of the access tier constitutes the lion’ share of the total power consumption due to the vast amount of devices in the network. The access network is discussed, including the evolution to all-optical access networks and the concept of PONs. Chapter 2 introduces CDR circuits and highlights the importance of these circuits. Additionally, the performance measures and a brief overview of different CDR types are given. A PLL-based CDR proves to be the most favorable type for high speed optical communication systems. Although this type still has some drawbacks, they can be overcome by using digital PLL techniques. However, in practice these techniques are rarely implemented in a CDR because there are still some challenges that prevent the digital PLL techniques from reaching their full potential. These challenges are identified and solutions are proposed. This leads to a next-generation of high-speed and low-power Clock and Data Recovery circuits which will be digital, i.e. an All-Digital Clock and Data Recovery (AD-CDR). In Chapter 3, the non-linear operation of the CDR is investigated using describing function techniques in the phase domain. First, the stability and the phase noise are discussed for the case of an analog charge pump CDR. Next, the phase domain model is extended to the case of the proposed ADCDR. The phase noise and the robustness against long idle sequences are investigated. Finally, simulation results are discussed. An overview of the design of the proposed AD-CDR circuit is given in Chapter 4. It starts with the system architecture and is followed by an in-depth discussion covering the most critical building blocks. This also includes an elaborate comparison between the conventional and the newly proposed Inverse Alexander Phase Detector (PD). Chapter 5 discusses the implementation of an AD-CDR Application Specific Integrated Circuit (ASIC) in a 40 nm Low Power CMOS technology. The top-down approach starts with the description of the top-level implementation. Subsequently, the implementation of each building block is covered in detail. To demonstrate the correct operation and low power efficiency, measurements were performed and are presented in Chapter 6. The final chapter (Chapter 7) provides an overview of the foremost conclusions of the presented research. Finally, the calculations of the Linear Time-Variant (LTV) analysis of the AD-CDR model are included in Appendix A.