Research Explorer

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Researcher

Stefaan Verschuere

Awards & Distinctions

15 Results

2005

Upstream experiments on the gigabit PON physical medium layer

Dieter VerhulstYanchun YiXing-Zhi QiuStefaan VerschuereZhe LouPeter OssieurJohan BauwelinckXin YinJan Vandewege

2004

FSAN GPON upstream burst-mode transmission experiments

Xing-Zhi QiuPeter OssieurJohan BauwelinckYanchun YiDieter VerhulstStefaan VerschuereZhe LouWei ChenYves MartensXin Yin et al.

Prototyping of high speed optical front ends for realization of a GigaPON uplink

Yanchun YiDieter VerhulstStefaan VerschuereXing-Zhi QiuXin YinPeter OssieurJohan BauwelinckJan Vandewege

The integration and evaluation of GPON uplink optical Front Ends

Yanchun YiDieter VerhulstStefaan VerschuereZhe LouPeter OssieurJohan Bauwelinck

2003

A Java-Based Embedded Digital Signal Processing System

Zhe LouStefaan VerschuereJo PletinckxXing-Zhi QiuJan Vandewege

Bookchapter in Wseas Transactions on Computers

A Java-based embedded digital signal processing system

Zhe LouStefaan VerschuereJo PletinckxXing-Zhi QiuJan Vandewege

A novel low-memory SPIHT codec for embedded progressive wavelet-based image compression

Zhe LouXing-Zhi QiuStefaan VerschuereJo PletinckxJan Vandewege

An FPGA-based lab test bed for a Gigabit passive optical network

Stefaan VerschuereZhe LouYanchun YiDieter VerhulstXing-Zhi QiuJan Vandewege

Lab test bed development for evaluation of the GigaPON uplink performance

Zhe LouStefaan VerschuereYanchun YiDieter VerhulstXing-Zhi QiuJan Vandewege

Web-based embedded control platform

Zhe LouJo PletinckxStefaan VerschuereXing-Zhi QiuJan Vandewege

Web-based embedded control platform

Zhe LouJo PletinckxStefaan VerschuereX QIUJan Vandewege

2002

A fixed point optimisation scheme for direct form IIR filters

Jo PletinckxRik VlaminckStefaan VerschuereStijn BertremJan VandewegeS TEMMERMAN

A fixed point optimisation scheme for direct form IIR filters.

Jo PletinckxRik VlaminckStefaan VerschuereStijn BertremJan VandewegeS TEMMERMAN

Bookchapter in A series of Reference Books and Textbooks, Electrical and Computer Engineering Series, Recent Advances in Circuits, Systems and Signal Processing, 2002

FPGA based real-time constrained time area optimized IIR design using digital-serial arithmetic

Rik VlaminckJo PletinckxStefaan VerschuereStijn BertremJan VandewegeP BOETSG VANUYTSELS TEMMERMAN

FPGA based real-time constrained time area optimized IIR design using digital-serial arithmetic.

Rik VlaminckJo PletinckxStefaan VerschuereStijn BertremJan VandewegeP BOETSG VANUYTSELS TEMMERMAN

Bookchapter in A series of Reference Books and Textbooks, Electrical and Computer Engineering Series, Recent Advances in Circuits, Systems and Signal Processing, 2002