Research Explorer

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Researcher

Sara Van Langenhove

Awards & Distinctions

8 Results

2007

SVtL: System Verification through Logic: tool support for verifying sliced hierarchical statecharts

Sara Van LangenhoveAlbert Hoogewijs

2006

Protocol conformance through refinement mappings in Cadence SMV

Sara Van Langenhove

A1 Journal Article in BULLETIN OF THE BELGIAN MATHEMATICAL SOCIETY-SIMON STEVIN

SVtL: System Verification through Logic: tool support for verifying sliced hierarchical statecharts

Sara Van LangenhoveAlbert Hoogewijs

Towards the correctness of software behavior in UML : a model checking approach based on slicing

Sara Van LangenhoveAlbert Hoogewijs

2005

Protocol Conformance through Refinement Mappings in Cadence SMV

Sara Van Langenhove

UML-Based Approach to Developing Verified Embedded Software

Sara Van Langenhove

2004

Integrating Cadence SMV in the Verification of UML Software

Sara Van LangenhoveAlbert Hoogewijs

UML based Verification of Software

Sara Van LangenhoveAlbert HoogewijsBenjamin De Leeuw