Research Explorer

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Researcher

Karel Heyse

18 Results

2015

Avoiding transitional effects in dynamic circuit specialisation on FPGAs

Karel HeyseDirk Stroobandt

Enabling FPGA routing configuration sharing in dynamic partial reconfiguration

Brahim Al FarisiKarel HeyseKarel BruneelJoão CardosoDirk Stroobandt

A1 Journal Article in DESIGN AUTOMATION FOR EMBEDDED SYSTEMS

Estimating circuit delays in FPGAs after technology mapping

Berg SeverensElias VansteenkisteKarel HeyseDirk Stroobandt

FASTER: facilitating analysis and synthesis technologies for effective reconfiguration

D PnevmatikatosK PapadimitriouT BeckerP BöhmA BrokalakisKarel BruneelC CiobanuTom DavidsonG GaydadjievKarel HeyseW LukX NiuI PapaefstathiouD PauO PellC PilatoMD SantambrogioD SciutoDirk StroobandtT TodmanElias Vansteenkiste

A1 Journal Article in MICROPROCESSORS AND MICROSYSTEMS

Identification of dynamic circuit specialization opportunities in RTL code

Tom DavidsonElias VansteenkisteKarel HeyseKarel BruneelDirk Stroobandt

A1 Journal Article in ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS

Improving the gain and reducing the overhead of dynamic circuit specialisation and microreconfiguration

Karel HeyseDirk Stroobandt

On the impact of replacing low-speed configuration buses on FPGAs with the chip’s internal configuration infrastructure

Karel HeyseJente BasteleusBrahim Al FarisiDirk StroobandtOliver KadlcekOliver Pell

A1 Journal Article in ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS

TCONMAP: technology mapping for parameterised FPGA configurations

Karel HeyseBrahim Al FarisiKarel BruneelDirk Stroobandt

A1 Journal Article in ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS

2014

Improving reconfiguration speed for dynamic circuit specialization using placement constraints

Amit KulkarniTom DavidsonKarel HeyseDirk Stroobandt

On the impact of replacing a low-speed memory bus on the Maxeler platform, using the FPGA's configuration infrastructure

Karel HeyseDirk StroobandtOliver KadlcekOliver Pell

Performance evaluation of dynamic circuit specialization on Xilinx FPGAs

Amit KulkarniKarel HeyseTom DavidsonDirk Stroobandt

Reducing the overhead of dynamic partial reconfiguration for multi-mode circuits

Brahim Al FarisiKarel HeyseDirk Stroobandt

2013

Efficient implementation of virtual coarse grained reconfigurable arrays on FPGAS

Karel HeyseTom DavidsonElias VansteenkisteKarel BruneelDirk Stroobandt

Efficient implementation of virtual coarse grained reconfigurable arrays on FPGAs

Karel HeyseTom DavidsonElias VansteenkisteKarel BruneelDirk Stroobandt

Proving correctness of regular expression matchers with constrained repetition

Karel HeyseKarel BruneelDirk Stroobandt

A1 Journal Article in ELECTRONICS LETTERS

2012

Automating reconfiguration chain generation for SRL-based run-time reconfiguration

Karel HeyseBrahim Al FarisiKarel BruneelDirk Stroobandt

Mapping logic to reconfigurable FPGA routing

Karel HeyseKarel BruneelDirk Stroobandt

2011

Memory-efficient and fast run-time reconfiguration of regularly structured designs

Brahim Al FarisiKarel HeyseKarel BruneelDirk Stroobandt