Research Explorer

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Researcher

Harald Devos

Awards & Distinctions

45 Results

2010

A parallel for loop memory template for a high level synthesis compiler

Craig Truett MooreWim MeeusHarald DevosDirk Stroobandt

Applying parameterizable dynamic configurations to sequence alignment

Tom DavidsonKarel BruneelHarald DevosDirk Stroobandt

Developing memory templates for high level synthesis compilers

Craig Truett MooreWim MeeusHarald DevosDirk Stroobandt

Towards a tighter integration of generated and custom-made hardware

Harald DevosWim MeeusDirk Stroobandt

2009

CLooGVHDL and JCCI

Harald DevosWim MeeusDirk Stroobandt

Optimizing the FPGA memory design for a Sobel edge detector

Craig Truett MooreHarald DevosDirk Stroobandt

Optimizing the FPGA memory design for a Sobel edge detector

Craig Truett MooreHarald DevosDirk Stroobandt

2008

Building an Application-specific Memory Hierarchy on FPGA

Harald DevosJan Van CampenhoutDirk Stroobandt

Constructing application-specific memory hierarchies on FPGAs

Harald DevosJan Van CampenhoutIngrid VerbauwhedeDirk Stroobandt

A2 Journal Article in TRANSACTIONS ON HIGH-PERFORMANCE EMBEDDED ARCHITECTURES AND COMPILERS

Embedding smart buffers for window operations in a stream-oriented C-to-VHDL compiler

Fabian DietErik H. D'HollanderKristof BeylsHarald Devos

FPGA Resource Estimation for Loop Controllers

Tom DegryseHarald DevosDirk Stroobandt

FlexWare project invites you to an open user group meeting on December 16th

Editorial material

High-level synthesis for data-intensive applications

Harald DevosDirk Stroobandt

Loop Transformations for the Optimized Generation of Reconfigurable Hardware

Harald DevosD StroobandtJ Van Campenhout

Loop Transformations to Reduce the Dynamic FPGA Reconfiguration Overhead

Tom DegryseKarel BruneelHarald DevosDirk Stroobandt

Reducing the dynamic FPGA reconfiguration overhead

Tom DegryseKarel BruneelHarald DevosDirk Stroobandt

Reducing the dynamic FPGA reconfiguration overhead with loop transformations

Tom DegryseKarel BruneelHarald DevosDirk Stroobandt

2007

07041 Working Group -- Towards Interfaces for Integrated Performance and Power Analysis and Simulation

C BLEAKLEYT CLERCKXHarald DevosM GRUMERA JANEKP STANLEY-MARBELLC STEGERV VENKATACHALAMM WENDTL BENINI et al.

Energy Scalability and the RESUME Scalable Video Codec

Harald DevosH EECKHAUTM CHRISTIAENSDirk StroobandtL BENININ CHANGU KREMERC PROBST

FPGA design methodology for a wavelet-based scalable video decoder

Hendrik EeckhautHarald DevosPhilippe FaesMark ChristiaensDirk Stroobandt

Finding Bounds on Ehrhart Quasi-Polynomials

Harald DevosJan Van CampenhoutDirk Stroobandt

Finding and applying loop transformations for generating optimized FPGA implementations

Harald DevosKristof BeylsMark ChristiaensJan Van CampenhoutErik D'HollanderDirk Stroobandt

Loop Controller Area Estimation for Automatic Design Space Exploration

Tom DegryseHarald DevosDirk Stroobandt

Loop Controller Area Estimation for Automatic Design Space Exploration

Tom DegryseHarald DevosDirk Stroobandt

RESUMEs wavelet-based scalable video decoder

H EECKHAUTM CHRISTIAENSHarald DevosP FAESDirk Stroobandt

Scalable, wavelet-based video: From server to hardware-accelerated client

Hendrik EeckhautHarald DevosPeter LambertDavy De SchrijverWim Van LanckerV NOLLETP AVASARET CLERCKXF VERDICCHIOMark Christiaens et al.

A1 Journal Article in IEEE TRANSACTIONS ON MULTIMEDIA

The energy scalability of wavelet-based, scalable video decoding

Hendrik EeckhautHarald DevosDirk Stroobandt

2006

From Loop Transformation to Hardware Generation

Harald DevosK BEYLSM CHRISTIAENSJan Van CampenhoutDirk Stroobandt

Hardware Generation from the Polyhedral Model

Harald DevosK BEYLSM CHRISTIAENSJan Van CampenhoutDirk Stroobandt

Loop transformations for generating scalable hardware

Harald DevosDirk StroobandtJan Van Campenhout

2005

A hardware-friendly wavelet entropy codec for scalable video

Hendrik EeckhautHarald DevosBenjamin SchrauwenMark ChristiaensDirk Stroobandt

Hardware-Friendly Wavelet Entropy Codec for Scalable Video

Hendrik EeckhautHarald DevosBenjamin SchrauwenMark ChristiaensDirk Stroobandt

Implementing a Hardware-Friendly Wavelet Entropy Codec for Scalable Video

Hendrik EeckhautMark ChristiaensHarald DevosDirk Stroobandt

Improving Parallelism of a Hardware Friendly, Scalable Wavelet Entropy codec.

Hendrik EeckhautMark ChristiaensBenjamin SchrauwenHarald DevosDirk Stroobandt

Improving the Hardware Friendliness of a Wavelet Based Scalable Video Codec

Hendrik EeckhautDirk StroobandtHarald DevosMark Christiaens

A2 Journal Article in WSEAS Transactions on Systems

Loop transformations for generating scalable hardware

Modeling Subbands of a Wavelet Based Scalable Video Codec

Hendrik EeckhautDirk StroobandtHarald DevosMark Christiaens

2004

Complexity scalable motion compensated temporal filtering

T CLERCKXF VERDICCHIOA MUNTEANUY ANDREOPOULOSHarald DevosH EECKHAUTM CHRISTIAENSDirk StroobandtD VERKESTS PETER

Ever considered SystemC?

Harald DevosHendrik EeckhautBenjamin SchrauwenMark ChristiaensDirk Stroobandt

Reconfigurable hardware for a scalable wavelet video decoder and its performance requirements

Dirk StroobandtHendrik EeckhautHarald DevosMark ChristiaensF VERDICCHIOP SCHELKENS

A1 Journal Article in COMPUTER SYSTEMS: ARCHITECTURES, MODELING, AND SIMULATION

Scalable and Hardware-friendly Wavelet Entropy Coding

Hendrik EeckhautMark ChristiaensHarald DevosBenjamin SchrauwenDirk Stroobandt

2003

An exploration of synchronization solutions for parallel short-range optical interconnect in mesochronous systems

Harald DevosJoni DambreWim MeeusDirk StroobandtJan Van Campenhout

Hardware implementation of an EAN-13 bar code decoder

Jeroen De MaeyerHarald DevosWim MeeusPeter VerplaetseDirk Stroobandt

Performance Requirements for Reconfigurable Hardware for a Scalable Video Decoder

Harald DevosHendrik Eeckhaut

Performance Requirements for Reconfigurable Hardware for a Scalable Wavelet Video Decoder

Harald DevosHendrik EeckhautMark ChristiaensF VERDICCHIODirk StroobandtP SCHELKENS